A known charge-pumped PLL 10 is shown in FIG. 1 and includes a phase frequency detector (PFD) 11 that accepts as inputs a reference signal and a feedback signal. The PFD has an “up” output and a “down” output that are connected to a charge pump 12, which drive a filter 13. The voltage output of the filter 13 controls the frequency of a voltage-controlled oscillator (VCO) 14. The output of the VCO 14 is taken as the output of the PLL and is also fed back to a feedback divider 16 that divides the frequency of the VCO output. The output of the feedback divider 16 is the feedback signal supplied to one input of the PFD 11.
In use, the PFD 11 modulates the up and down pulse signals depending upon whether the feedback signal is leading or lagging the reference signal. The up and down pulses are continuously generated such that when the feedback signal is in phase with the reference signal the pulses of the up and the down signals have the same width. If the feedback signal begins to lag the reference signal, then the pulse width of the up signal is increased. If the feedback signal begins to lead the reference signal, then the pulse width of the down signal is increased. Thus the duty cycle of the up or down signals is varied in accordance with the phase or frequency difference of the signals input to the PFD.
The outputs of the PFD 11 are integrated by an integrator 15 to produce a control voltage. The integrator 15 comprises the charge pump 12 and the filter 13. The up and down pulses are translated into a current by the charge pump, which either forces current into or out of the filter, which may be a loop filter. The filter integrates the current and generates a control voltage that is input to the VCO.
For a PLL to lock onto a reference signal, the frequency divider 16 must function up to the VCO maximum frequency. Due to process, voltage and temperature (PVT) variations, the VCO maximum frequency may be much higher than the desired output frequency of the PLL. Hence the feedback divider 16 will be required to have an equally high maximum input frequency. The problem is exacerbated in applications where high-resolution is desirable, in these cases complex division circuitry may be needed, which typically has a relatively lower frequency response.
In these PLLs, it is necessary to design the feedback divider so as to have an appropriate input frequency range, according to the properties of the Voltage Controlled Oscillator (VCO). Further, the feedback divider determines the frequency resolution of the PLL, and the output frequency of the VCO. The smaller the division factor N in the feedback divider, the finer the resolution of the PLL output frequency. However, a small division factor N gives a lower output frequency.
Embodiments of the present invention may decorrelate the VCO maximum frequency from the divider complexity. Removing this design constraint will reduce the design time required to generate a PLL for a specific use.
Embodiments of the present invention may provide a PLL that has both a fine frequency resolution and a maximum output frequency close to the VCO maximum output frequency.